The present invention relates to methods and systems of performing an analysis on integrated circuit designs, and more particularly to methods and systems that utilize regions (buckets) to evaluate different portions of a given circuit design.
As described in U.S. Pat. No. 7,337,420 (the complete disclosure of which is incorporated herein by reference) stress can be applied in semiconductor devices to increase the mobility of electrons or holes in such devices. For example, stress can be applied to the channel of field effect transistors (FETs) by using intrinsically stressed films such as the liner film that is used normally in the formation of metal contact (MC) terminals to the source and drain regions of the FET. Stress films can typically be nitride films because nitride films are compatible with the silicon fabrication process steps used for contact formation and etching. Liner films exert stress on an isolated FET gate (also called the “victim” gate) by adhering to adjacent surfaces such as the wafer surface and “pushing” or “pulling” on the gate structures. The stress is transferred primarily through the gate spacers, which are self-aligned to the gate polysilicon (PC). A liner-film with inherent tensile stress transfers tensile stress, and is used for improving electron mobility in n-type FETs (NFETS), while a liner film with inherent compressive stress transfers compressive stress, and is used for improving hole mobility in p-type FETs (PFETs).
As described in U.S. Pat. No. 7,337,420, one factor that dilutes the effectiveness of nitride liners is that the contact metallurgy, particularly to the source and drain regions, requires parts of the liner to be etched away very near the device. This not only disrupts the ability of the long film runway to transfer stress, but also moves the singularity/edge that would influence the channel further away, severely reducing the stress benefit. Other structures that are on the same physical level above the silicon surface such as contact metallurgy and that interrupt the film can also have the same effect. An example of such a structure is polysilicon wiring.
As described in U.S. Pat. No. 7,337,420, an even more serious concern is that these structures can be arbitrarily designed and therefore have a difficult predicting effect on performance, either positive or negative. Layout-dependent factors that influence the stress include the spacing between the victim gate and adjacent structures, the dimensions of these adjacent structures, the amount of contact coverage (or source/drain strapping), and in the case of dual-stress liner technologies (one liner for NFETS and a different liner for PFETS), the proximity of the interface between the two liner films. Small changes in FET layout can introduce noticeable shifts in drive current, and this variation can appear to change device to device across a chip. Not accounting for this magnitude of variation in stress benefit can seriously underpredict or overpredict electrical performance in circuit simulation. Furthermore, with information about the influence of stress on a given layout, circuit designers can optimize their designs for exploiting stress.